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Atomic Phoenix - Brown Gas generator project

Written by Robert Greenyer on .

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0 #19 David W. Davis 2020-03-22 21:56
Glad to hear the progress SysEngineer.
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+1 #18 Robert Greenyer 2020-03-22 17:38
Several updates to live document.
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0 #17 Robert Greenyer 2020-03-16 12:42
GlobalBEM 2013 Conference Presentation by Moray B. King

youtu.be/GhZ1reCoyrY
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+2 #16 David W. Davis 2020-03-07 16:20
I will add a comment to Bob's last mention on vibration, harmonics and transmutation. I was involved with a vacuum tube production problem with what we called plasmoid formation, aka EVO's. One of those things that came from the investigation was micron and sub micron surface topology. Secondary was carbon contamination. Sound familiar? Carbon contamination was minimal. The surface was nearly glass smooth on examination. We wanted to eliminate the EVO's. The fix addressed both suspect issues. Sand blasting the surface to create 1 to 5 micron topology features and in effect removing adhered carbon. EVO's went away and never returned.
We will need SEM/EDS to better characterize what is happening with the BG plates and particularly the floating plates after break in. While transmutation is important, I want to understand molecular formation at and in the vicinity of the plates. I expect to see a self organized topology that could be revealing on differences in various HHO configurations and efficiencies.
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0 #15 Robert Greenyer 2020-03-06 22:03
Hi John,

May be worth acquiring the spare panel, thanks for finding that.
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0 #14 Robert Greenyer 2020-03-06 22:00
Hi Guys,

Here are the photos David W. Davis sent me.

drive.google.com/.../

drive.google.com/.../

If any of you want to have access to the live document to add details of components or edit it in other areas, please make a request.

Also, I can provide a common server space for people to exchange files easily, let me know if you are interested.
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+3 #13 Stevenson 2020-03-06 18:24
The CPU board is a relatively simple 2 layers PCB with very straight traces, so it would not be too difficult to derive the schematic: this would simplify a lot the work and will give some clues for understanding the code. To this end it would suffice a good quality high resolution picture of both sides of the board.
My guess is that the program control loop runs on polling for most of the external resources, due to non critical timings, and perhaps employs the external interrupt for the ADC only. If we can get the schematic we can figure out the peripheral addresses and so link the code to its activity and purpose. Without the schematic this task is quite hard, IMO.
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0 #12 David W. Davis 2020-03-06 17:07
Not to be critical... Just painful experience as reference.
Cheers
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0 #11 David W. Davis 2020-03-06 17:02
Quoting Mats002:
Ok, so we have a measure of electrolyzer current
going into the ADC going to the microprocessor as
8 bit(?) resolution. What can output be? A control
signal to the DC electrolyzer? DA conversion can
be constructed very simple, no need for a chip.

Ok. So speculation just slows us down until we can get a good schematic down. Current is key measure, you have to have the overall picture before understanding and interpreting the details.
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0 #10 Mats002 2020-03-06 16:13
Ok, so we have a measure of electrolyzer current
going into the ADC going to the microprocessor as
8 bit(?) resolution. What can output be? A control
signal to the DC electrolyzer? DA conversion can
be constructed very simple, no need for a chip.
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+1 #9 SYsEngineer 2020-03-06 15:34
Thanks for the LS28 note -- for some reason, I was not able to find it is a 74LS family list.

The ADC is an 8-channel ADC. I know that the panel board gets the current (voltage across a shunt) and voltage signals from the heavy current electrolyzer. However, they are both directly displayed by a meter chip tied to the panel displays. So far, just the current signal (conditioned by op-amps) goes to the ADC. The voltage signal seems to be ignored.
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0 #8 David W. Davis 2020-03-06 15:30
Quoting Mats002:
Is there any trace of A/D and D/A conversion? The logic kan be a signal processor. If so there is little code and lots of data in the EPROM.

There is and ADC on the board.
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+2 #7 David W. Davis 2020-03-06 15:28
I have sent photos to Greenyer till I can figure out how to post pics here.
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+1 #6 Mats002 2020-03-06 15:27
Is there any trace of A/D and D/A conversion? The logic kan be a signal processor. If so there is little code and lots of data in the EPROM.
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+1 #5 David W. Davis 2020-03-06 15:15
The 74LS28 is a quad 2 input positive NOR bufers. Can send phoro of document on the part. How?
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-1 #4 SYsEngineer 2020-03-06 14:34
There is a chip on the board labeled 74LS 28 with a symbol that is not a common manufacturer. It is somehow involved in the address decoding -- I have no idea what s is. The closest chip I have found is a LS280 -- parity tree. Anyone have any idea what it is?
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+1 #3 SYsEngineer 2020-03-06 14:13
I based the idea that there is only one interrupt on the decoded assembly listing. It is now apparent that I need to trace the board more thoroughly to verify that. It also seems to use memory-mapped IO (based on addresses that I se dis-assembled).

I have now powered up the system and get some activity, but except for reset, do not see any response to pushbuttons on the panel.
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+1 #2 Robert Greenyer 2020-03-06 13:23
Hi David,

Well, people were only directed here last night.

I will ask the systems engineer to communicate here. Files can be uploaded here as needed.
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+1 #1 David W. Davis 2020-03-06 12:01
I don't see any comments here yet. I saw some of the developer's video on Radare, yes steep learning curve.

Saw mention of only a single interrupt.
This indicates to me the developer established his own external interrupt architecture. There will be some logic to capture which event occurred and some value associated with it.
When the circuit is chased down to some level of a schematic, let me know if you need help deciphering the logic. I designed a number of systems using TTL logic back in that era.
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